Introduction to Incremental Encoders

This article is a short tutorial about incremental encoders and incremental encoder interfaces.  It discusses the operation and construction of incremental encoders, as well as some important design considerations for the incremental encoder interface.

Introduction to Incremental Encoders
An incremental encoder is an electromechanical device that produces digital pulses in response to mechanical displacement. Most encoders employ a light source, a disk that rotates about a shaft, and a photodetector to generate the requisite pulses. The rotating disk has alternating opaque and transparent regions which serve to block the light or pass it through to the detector. As the disk rotates, the detector receives light pulses, thus causing it to produce electrical pulses. The shaft, in turn, is mechanically connected to a mechanical device that is to be instrumented so that its speed and/or position can be monitored.

As the disk rotates faster, the pulse frequency increases accordingly. Since the relationship between pulse frequency and rotational velocity is linear, it is a simple matter to use the pulse frequency as an indication of speed.  The output pulses can be transformed into speed units by measuring their frequency, and then multiplying the frequency by an appropriate scale factor.

While one output pulse stream is useful for measuring speed, it does not indicate the direction of rotation (i.e., clockwise vs. counter-clockwise) of an incremental encoder. To get around this problem, an incremental encoder will contain two rotating disks, both mounted to a common shaft, so that two pulse streams will be produced simultaneously.  These two pulse streams (aka “clocks”) can be used to determine both velocity and direction.  This is made possible by an intentional misalignment of the two disks that causes a 90 degree phase difference between their clocks. An incremental encoder that produces two clocks (typically designated A and B) having a 90 degree phase difference is said to be “quadrature” encoded.

In the case of a quadrature incremental encoder, the A clock phase will lead B for one direction of rotation, and B will lead A when the encoder rotates in the opposite direction. A quadrature encoder’s rotational direction can be determined by detecting the phase relationship between the A and B clocks, while its speed can be detected by measuring the frequency of either clock.

It is possible to obtain more precise velocity measurements from a quadrature incremental encoder by “multiplying” the clock frequency.  This is accomplished by counting clock edges instead of clock pulses. Each clock has both a rising edge and a falling edge for each pulse, so by counting all edges of both the A and B clock phases, it is possible to get four times the resolution one would get by simply counting pulses from the A clock.

In addition to the clock outputs, some incremental encoders also produce an “index” signal.  This signal consists of a single pulse that occurs at a reference position on the encoder’s shaft.

The Incremental Encoder Interface
In its simplest form, an incremental encoder interface consists of a lone up/down counter and, in fact, even the most sophisticated incremental encoder interface has an up/down counter at its core.  This counter is fundamental to all incremental encoder interfaces because its current state--the accumulated counts value--can be used to determine both the position and direction of motion of the instrumented mechanical system.

Encoder position is determined by the instantaneous counts value.  The encoder counter increments when the encoder turns one direction and it decrements when the encoder turns the other direction.  At any given moment, the counts value indicates the current encoder position.

Encoder speed is determined by sampling the instantaneous counts value twice, at different times.  The speed is then computed by taking the difference between the sample values and dividing this difference by the elapsed time between samples.  This gives the average speed in the time interval between samples.

Design Considerations
Incremental encoders are used in measurement and control systems, and such systems are usually controlled by a CPU.  Since the encoder counter is typically sampled by a CPU, and CPUs have other responsibilities besides sampling encoder counts, there are some special considerations to take into account when designing incremental encoder interfaces.

Resolution: An encoder counter has finite resolution, measured in bits. For example, a four bit counter has sixteen possible states. Suppose for a moment that an incremental encoder is rotating in only one direction, and the CPU must periodically sample the counts so as to know the position.  A four bit counter will overflow every sixteen counts, so the CPU must therefore sample counts faster than the worst-case overflow rate to avoid losing track of the position. If the encoder is allowed to move in both directions, the CPU must sample counts twice as fast.  Clearly, higher counter resolution results in less demand on the CPU. In many applications, 24 bits is a practical minimum.  For high speed and/or high precision applications, 32 bit resolution is recommended.

Integrity: The CPU data path is not always a perfect match for the counter resolution. For example, an application might have a 32 bit encoder counter that is accessed by an 8 or 16 bit CPU.  In such cases, it is important that the counts value not change in the middle of a counts transfer to the CPU.  To ensure this, an incremental encoder interface should double buffer the counts in a holding register.  When the CPU is ready to read the counts, it writes to a control register to cause the counts to be synchronously transferred to the holding register. The CPU can then read the counts from the holding register, either all at once or in pieces, at its leisure, without the risk of receiving corrupted data.

Speed: To ensure glitch-free operation, an incremental encoder interface must be a fully synchronous digital design. Since the encoder clock signals are asynchronous with respect to the interface clock, the encoder clocks must be synchronized to the system clock before they are passed into the interface’s core logic.  Sampling theory dictates that the system clock frequency must be greater than the highest event frequency, and since the events of interest are encoder clock edges, the system clock must have a frequency greater than four times that of the encoder’s A clock frequency. In practice, the system clock frequency must be even higher than this because encoder clocks never have exactly 90 degrees phase difference.  Because the incremental encoder interface is a synchronous design, the encoder counter must be capable of counting at the system clock rate.

Preload: As mentioned earlier, the CPU has responsibilities other than servicing the incremental encoder interface.  A worthy incremental encoder interface can make the CPU’s job easier by performing a few select real time functions that would be difficult or impossible for the CPU to perform. One of these functions is counter preload, which causes the counter to be loaded with a specified value upon overflow or underflow, or in response to an additional input signal.  Another useful function is a “gate” input that enables counting only when the gate signal is active.  The gate input can then be connected to a pulse generator to implement a frequency counter or pulse width measurement function.

Sensoray Solutions
Sensoray offers a number of products that include incremental encoder interfaces.  These interface designs account for all of the technical issues mentioned in this article, and many of our interfaces include additional features beyond those described in this article. For more details, visit our Encoder Interfaces page or view the online datasheets for the following models:
 

ISA: 421 and 425
PC/104: 526
PCI: 626
Ethernet: 2620
STD: 7421